Versatile signal detector circuit using common mode shift with all-pass characteristics
US10826810B1 · kind B1 · utility
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6References
12Claims
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Key dates
| Filing date | Sep 30, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Sep 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus in a receiver to determine if a high speed communication link is in an idle mode or in an active mode. Signals during the idle mode are of lower amplitude and lower frequency compared to amplitude and frequency in the active mode. A signal detector in the receiver determines if the high speed communication link has transitioned from idle mode to active mode and, if so, wakes up high power circuitry in the receiver to receive data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.