Patent · US Active

Packet processing architecture and method therefor

US10826982B2 · kind B2 · utility

0Cited by
5References
12Claims
0Family size

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Inventors

Key dates

Filing dateJan 10, 2013
Grant dateNov 3, 2020
Priority date
Expiry dateSep 3, 2034

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH04L69/321
  • WIPO fieldDigital communication
  • WIPO sectorElectrical engineering

Abstract

A packet processing architecture includes a plurality of packet processing stages, wherein at least one of the packet processing stages includes multiple next processing stage modules that are operably coupled to respective further processing stages, wherein the multiple next processing stage modules are dynamically configurable.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.