Reduction of insertion loss in printed circuit board signal traces
US10827627B2 · kind B2 · utility
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1References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Mar 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4673
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A printed circuit board, according one embodiment, includes a reference layer; a dielectric layer disposed on the reference layer; and a conductor layer adhered to the dielectric layer with an adhesive layer disposed between the dielectric layer and the conductor layer. The conductor layer has a smooth surface facing the dielectric layer having a roughness (Rz) of less than two microns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.