Status derivation of load circuit via capacitance
US10830831B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2016 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Jun 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05B45/50
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Apparatuses (10) for determining statuses of load circuits (11) comprise terminals (1, 2) for exchanging current signals with current sources (12). The load circuits (11) comprise D loads (L1-LD) in series combinations coupled to the terminals (1, 2). The apparatuses (10) further comprise capacitance circuits (3) comprising E monitor capacitances (CM1-CME) with first contacts coupled to each other and to one of the terminals (1, 2) and second contacts coupled to interconnections between the loads (L1-LD). The apparatuses (10) further comprise detection circuits (4) for detecting voltage signals present between the first and second terminals (1, 2), and derivation circuits (5) for deriving the statuses of the load circuits (11) from the detected voltage signals. Thereto, the derivation circuits (5) may calculate instantaneous capacities comprising steps indicative for said statuses of the load circuits (11). The capacitance circuits (3) do advantageously not interfere with the load circuits (11) in steady-states, and may further comprise F parallel capacitances (CP1-CFP) in parallel to the loads (L1-LD).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.