Power efficiency-aware node component assembly
US10831252B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2017 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | May 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3296
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Sub-components assembled into a computer are selected based on sub-component power efficiency levels (for example, low, medium, high) and/or anticipated usage of the computer. Multiple units of each type of sub-component (for example, a CPU) are tested to determine a power efficiency level of each unit. Computers in which sub-component efficiency levels are desired to match an overall computer efficiency level, receive sub-component units of corresponding efficiency level. Computers anticipated to run applications that make intensive use of a given type of sub-component receive the given units having a higher efficiency level. Computers anticipated to run applications that make little use of a given type of sub-component receive a physical unit having a lower efficiency level. Computers anticipated to run a wide variety of applications of no particular usage intensity for a given type of sub-component, receive a unit having an average efficiency level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.