Flash-based accelerator and computing device including the same
US10831376B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 11, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Sep 20, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash-based accelerator configured to be connected to a host including a CPU and a system memory is provided. A plurality of processors execute a plurality of kernels offloaded from the host. A memory system includes a first memory that is used to map a data section of each kernel to the flash memory. A supervisor processor maps a region of the first memory pointed by a data section of a first kernel to a region of the flash memory to allow first data to move between the region of the first memory and the region of the flash memory, based on a first message which is transferred in accordance with execution of the first kernel by a first processor among the plurality of processors. A network integrates the flash backbone, the memory system, the plurality of processors, and the supervisor processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.