Multimodal digital multiplication circuits and methods
US10831445B1 · kind B1 · utility
4Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Sep 20, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Sep 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure pertain to multimodal digital multiplier circuits and methods. In one embodiment, partial product outputs of digital multiplication circuits are selectively inverted based on a mode control signal. The mode control signal may be set based on a format of the operands input to the multiplier. Example embodiments of the disclosure may multiply combinations of signed and unsigned input operands using different modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.