Configuration load of a reconfigurable data processor
US10831507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Feb 26, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.