Memory address translation
US10831673B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Dec 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory address translation apparatus comprises page table access circuitry to access page table data to retrieve translation data defining an address translation between an initial memory address in an initial memory address space, and a corresponding output memory address in an output address space; a translation data buffer to store, for a subset of the virtual address space, one or more instances of the translation data; and control circuitry, responsive to an input initial memory address to be translated, to request retrieval of translation data for the input initial memory address from the translation data buffer and, before completion of processing of the request for retrieval from the translation data buffer, to initiate retrieval of translation data for the input initial memory address by the page table access circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.