Multi-tier cache placement mechanism
US10831678B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2017 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Jul 31, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Storage of data in a cache system is controlled by a cache monitor. A cache line is filled in response to a memory instruction from a cache client. The cache monitor includes a predictor table and update logic. An entry in the predictor table comprises an instruction identifier that associates the entry with a memory instruction and, for each cache in the system, a reuse counter. The update logic is configured to update a reuse counter table dependent upon cache behavior in response to memory instructions. Storage of data a first data address in cache in response to a memory instruction having a first instruction identifier, is dependent upon reuse counter values in an entry of the predictor table associated with first instruction identifier. Reuse counters are updated dependent upon cache behavior. A Bloom filter or other data structure may be used to associate data addresses with a memory instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.