Patent · US Active

Prediction of closure feasibility in microprocessor design

US10831955B1 · kind B1 · utility

1Cited by

12References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Matthew A. Cooke · Cedar Park, US
Zhichao Li · Austin, US
Kai Liu · Haverhill, US
Su Liu · Round Rock, US
Manjunath Ravi · Austin, US

Key dates

Filing date	Nov 19, 2019
Grant date	Nov 10, 2020
Priority date	—
Expiry date	Nov 19, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for predicting post-placement timing-analysis results includes obtaining, for a logic design, logic-synthesis data and logic-planning data. The method also includes inputting, into a neural network, the logic-synthesis data and logic-planning data. The neural network is trained to correlate logic-synthesis data and logic-planning data with post-placement timing-analysis results. The method also includes receiving, from the neural network, predicted post-placement timing-analysis results.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.