Negative voltage generation for computer memory
US10832756B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2019 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Sep 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for negative voltage generation for a computer memory are described herein. An aspect includes enabling a first negative word line voltage (VWL) clock generator. Another aspect includes providing, by the first VWL clock generator, based on a clock signal, a first pump clock signal to a first VWL pump, and a second pump clock signal to a second VWL pump. Another aspect includes generating a VWL based on the first VWL pump and the second VWL pump, wherein the VWL is provided to a word line driver of a computer memory module. Another aspect includes comparing the VWL to a VWL reference voltage. Another aspect includes, based on the VWL being below the VWL reference voltage, disabling the first VWL clock generator, wherein the first VWL pump and the second VWL pump are disabled based on disabling the first VWL clock generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.