Method for precisely aligning backside pattern to frontside pattern of a semiconductor wafer
US10833021B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Jun 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D12/411
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method comprises the steps of providing a semiconductor device wafer; forming a first plurality of alignment marks on a first side of the semiconductor device wafer; forming a first pattern of a first conductivity type; forming a second plurality of alignment marks on a second side of the semiconductor device wafer; forming a bonded wafer by bonding a carrier wafer to the semiconductor device wafer; forming a third plurality of alignment marks on a free side of the carrier wafer; applying a grinding process; forming a plurality of device structure members; removing the carrier wafer; applying an implanting process and an annealing process; applying a metallization process and applying a singulation process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.