Low power 2D memory transistor for flexible electronics and the fabrication methods thereof
US10833102B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2019 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Mar 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices and methods of a transistor device that include a flexible memory cell. The flexible memory cell having a gate stack with sidewalls provided over a substrate. The gate stack including a metal gate layer provided over the substrate. A buffer layer provided over the metal gate layer. A ferroelectric layer provided over the buffer layer. A dielectric layer provided over the ferroelectric layer. Further, a two-dimensional (2D) material layer provided over a portion of a top surface of the dielectric layer. Source and drain regions provided on separate portions of the top surface of the dielectric layer so as to create a cavity that the 2D material layer are located.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.