Voltage sampling circuits
US10833659B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2017 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Dec 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40626
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A voltage sampling circuit arrangement comprises: an oscillator circuit portion arranged to produce a periodic oscillator output signal at an oscillation frequency dependent on a bias current provided thereto; a sampling circuit portion arranged selectively to connect an input terminal (Vin) to an output terminal (Vout) in response to an applied switching signal (Vswitch) derived from said oscillator output signal, wherein said sampling circuit portion has a current leakage dependent on temperature; and a biasing circuit portion arranged to provide said bias current to the oscillator circuit portion wherein said bias current is dependent on temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.