Semiconductor device
US10833673B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 7, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Feb 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An operation adjustment method of an SOI device comprises steps of: (a) obtaining a drain current-substrate bias voltage characteristic of an NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of a PMOS transistor as a voltage obtained by subtracting a built-in potential of a pn junction from the lowest substrate bias voltage; and (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit. Reduction in the power consumption and maintenance of the radiation tolerance are both achieved for the SOI device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.