Method and circuits for reducing noise in phase-locked loops
US10833684B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2020 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Jan 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) includes: a phase frequency detector configured to: generate one or more comparison signals indicating whether a reference input signal is leading a feedback signal or whether the feedback signal is leading the reference input signal; a charge pump coupled to the phase frequency detector and configured to convert the one or more comparison signals into a driving current; a loop filter coupled to the charge pump and configured to split the driving current to generate a first voltage signal and a second voltage signal; and a voltage controlled oscillator coupled to the loop filter and configured to: receive the first voltage signal and generate a first control current; receive the second voltage signal and generate a second control current; and combine the first and second control currents to jointly drive a charge controlled oscillator such that the output signal of a desired frequency is generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.