Image sensor having separate, stacked, pixel array, DRAM, and logic/analog-digital converter integrated circuit die
US10834347B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Nov 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/811
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multiple IC, buffered, image sensor has a first IC with pixels, selection transistors, and interconnect coupling selected pixels with first inter-die bond pads that convey image data to a second IC having logic and ADCs. The ADCs having inputs coupled to selected pixels and outputting through-silicon vias and inter-die bond pads to a third IC coupled to buffer raw image data in DRAM. A method includes capturing images with array pixel IC divided into sub-arrays each coupled to a separate, associated, ADC through inter-die bonds, scanning the sub-arrays and converting the image data to digital image data; and transferring the digital image data over inter-die bonds into buffers in DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.