Configurable interface alignment buffer between DRAM and logic unit for multiple-wafer image sensors
US10834352B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2019 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Jan 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/802
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image sensor has an array of pixels configured in multiple blocks; each block coupled to a separate analog-to-digital converter (ADC) to provide digitized image data. The ADCs feed digitized images into an image RAM; and the image RAM feeds digitized images to an alignment buffer in a first pixel order. The alignment buffer provides digitized images to an image processor in a second pixel order different from the first pixel order. In an embodiment, the alignment buffer uses a multiport RAM. In another embodiment, the alignment buffer uses first and second alignment buffer RAMs, writing one alignment buffer RAM while reading the other alignment buffer RAM to provide image data to the image processor. In embodiments, the alignment buffer provides digitized images in an order selectable between a full resolution and a reduced resolution order, and selectable between a right-to-left and left-to-right order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.