Multi-layer integrated circuits having isolation cells for layer testing and related methods

US10838003B2 · kind B2 · utility

Assignee

• Duke University · US

Inventors

• Krishnendu Chakrabarty · Chapel Hill, US
• Ran Wang · Durham, US

Key dates

• Filing date: Jun 17, 2019
• Grant date: Nov 17, 2020
• Expiry date: Jun 17, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Multi-layer integrated circuits having isolation cells for layer testing and related methods are disclosed. According to an aspect, an integrated circuit includes multiple isolation cells. Example isolation cells include, but are not limited to, electronic fuses and tri-state flip-flops. The integrated circuit also includes a first layer having first and second sets of electronic components, the first set of electronic components being operatively connected to the second set of electronic components via the isolation cells. Further, the integrated circuit includes multiple transmission gates associated with the isolation cells. The integrated circuit also includes a second layer having electrical circuitry operatively connected to the electronic components of the first layer. The electrical circuitry is configured to apply test patterns to the electronic components of the first layer. Further, the electrical circuitry is configured to receive test responses from the electronic components of the first layer through the vias.