Memory controller, storage device, information processing system, and memory control method
US10838887B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2016 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Jun 21, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
High-speed data transfer is performed in a storage device having a plurality of semiconductor memories while an increase in power consumption is prevented.In a memory controller, a request transfer unit transfers a request for demanding transfer of data and data based on the request to each of a plurality of memories in synchronization with a clock signal. A busy time measurement unit measures a busy time which is a time required for access based on the request, for a selected memory which is one memory out of the plurality of memories. A clock signal adjustment unit substantially equalizes the measured busy time of the selected memory and a total time required for transferring the requests and the data for the plurality of memories except the selected memory by adjusting a frequency of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.