Systems and methods for systolic array design from a high-level program
US10838910B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2018 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Aug 1, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for automated systolic array design from a high-level program are disclosed. One implementation of a systolic array design supporting a convolutional neural network includes a two-dimensional array of reconfigurable processing elements arranged in rows and columns. Each processing element has an associated SIMD vector and is connected through a local connection to at least one other processing element. An input feature map buffer having a double buffer is configured to store input feature maps, and an interconnect system is configured to pass data to neighboring processing elements in accordance with a processing element scheduler. A CNN computation is mapped onto the two-dimensional array of reconfigurable processing elements using an automated system configured to determine suitable reconfigurable processing element parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.