Systems and methods for accurate voltage impact on integrated timing simulation
US10839123B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Feb 28, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for simulating an integrated circuit system. A file representative of an integrated circuit design is received, the integrated circuit design including a plurality of cells and characteristics of power supply and ground paths to each cell. A vulnerable cell of the integrated circuit design based on a vulnerability metric of the vulnerable cell. A power analysis of a portion of the integrated circuit design is performed to determine a plurality of power and ground levels within a timing window for each of a plurality of cells including the vulnerable cell. A timing analysis of the vulnerable cell is performed, where the timing analysis receives a single power level and single ground level for the vulnerable cell and determines a slack level for the vulnerable cell. An at risk path is identified based on the vulnerable cell slack level, and a dynamic power/ground simulation of one or more cells in the at risk path is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.