Memory cell with charge trap transistors and method thereof capable of storing data by trapping or detrapping charges
US10839893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Aug 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a first charge trap transistor and a second charge trap transistor. The first charge trap transistor has a substrate, a first terminal coupled to a first bitline, a second terminal coupled to a signal line, a control terminal coupled to a wordline, and a dielectric layer formed between the substrate of the first charge trap transistor and the control terminal of the first charge trap transistor. The second charge trap transistor has a substrate, a first terminal coupled to the signal line, a second terminal coupled to a second bitline, a control terminal coupled to the wordline, and a dielectric layer between the substrate of the second charge trap transistor and the control terminal of the second charge trap transistor. Charges are either trapped to or detrapped from the dielectric layer of the first charge trap transistor when writing data to the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.