Planarization and flip-chip fabrication process of fine-line-geometry features with high-roughness metal-alloyed surfaces
US10840106B2 · kind B2 · utility
0Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Oct 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/81815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of semiconductor device fabrication that enables fine-line geometry lithographic definition and small form-factor packaging comprises: forming contacts on a metal layer of the semiconductor device; applying a protective mask layer over active regions and surfaces of the contacts having rough surface morphology; planarizing a surface of the semiconductor device until the protective mask layer is removed and the surfaces of the contacts having rough surface morphology are planarized; and forming contact stacks on the surfaces of the contacts which are planarized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.