Process for fabricating a heterostructure comprising a conductive structure and a semiconductor structure and including a step of electrical discharge machining
US10840110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2017 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Oct 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F71/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating at least one elementary heterostructure includes producing a heterostructure comprising at least one semiconductor structure of resistivity higher than or equal to 1 Ω.cm located between two electrically conductive structures of resistivity lower than or equal to 0.1 Ω.cm; cutting the heterostructure by electrical discharge machining so as to define at least the elementary heterostructure; the thickness of the semiconductor structure being smaller than about 1/10th of the thickness of at least one of the electrically conductive structures or of the total thickness of the electrically conductive structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.