Semiconductor device including a three-dimensional channel
US10840142B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2018 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Nov 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.