Vertical memory devices including stacked conductive lines and methods of manufacturing the same
US10840183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2020 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Apr 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n-1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n-1)-th extended gate lines serves as a pad region, and the pad regions have different areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.