Fully digital, static, true single-phase clock (TSPC) flip-flop
US10840892B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Jul 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a flip-flop (FF) (e.g., a D-type flip-flop (DFF) or a scan flip-flop (SFF)). The FF is configured to reduce dynamic power consumption of an integrated circuit (IC) by employing only a single-phase of a clock signal. Specifically, the FF includes a primary latch and a secondary latch. Each of these latches includes a multi-stage input driver, which internally generates a control signal based on both the single-phase clock signal and an input signal and which also generates a stored bit signal based on the control signal. Each of these latches can also include a feedback path with an inverter that inverts the stored bit signal and a tri-state logic device that generates a feedback signal that is dependent on the inverted stored bit signal, the control signal and the clock signal. As a result, the FF is a fully digital, static, true single-phase clock (TSPC) flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.