Patent · US Active

Clock alignment system having a dual-loop delay-locked loop

US10840917B1 · kind B1 · utility

10Cited by

0References

18Claims

0Family size

Assignee

BAE Systems Information and Electronic Systems Integration Inc. · US

Inventors

Joseph D. Cali · Nashua, US
Curtis M. Grens · Manchester, US
Richard L. Harwood · Westford, US
Gary M. Madison · Waltham, US
James M. Meredith · Westford, US
Zachary D. Schottmiller · Nashua, US
Randall M. White · Merrimack, US

Key dates

Filing date	Dec 9, 2019
Grant date	Nov 17, 2020
Priority date	—
Expiry date	Dec 9, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/093
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A clock alignment system includes a first clock generator generating a first clock signal in a first clock domain and a second clock generator generating a second clock signal in a second clock domain slower than the first clock domain. A coarse delay-locked loop (DLL) generates third clock signals having corresponding phase offsets from the first clock signal, and a fine DLL generates a fourth clock signal by adjusting the phase of a selected one of the third clock signals. The second clock generator generates the second clock signal from the fourth clock signal. A phase detector compares phases of the first and second clock signals. A control circuit aligns the first and second clock signals by using the compared phases to select the third clock signal output by the coarse DLL, and control the phase adjustment by the fine DLL of this third clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.