High efficiency power amplifier architectures for RF applications
US10840939B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Jul 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.