Hierarchical packing of syntax elements
US10841579B2 · kind B2 · utility
1Cited by
15References
20Claims
0Family size
Assignee
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Key dates
| Filing date | May 27, 2017 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Dec 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.