Processing system, related integrated circuit, device and method
US10845999B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 16, 2019 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Jan 16, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/44505
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware configuration circuit configured to sequentially read data packets and transmit the data to a configuration data client. The configuration data client configured to receive a first and a second set of configuration data addressed to a respective address. The client is configured to store the first set of configuration data in a register and verify whether further configuration data may be written to the respective register as a function of a type identification signal. In response, the configuration data client is configured to overwrite the first set of configuration data by storing the second set of configuration data in the respective register or maintain the first set of configuration data by inhibiting storage of the second set of configuration data received in the respective register. The configuration corresponding to verifying whether further configuration data may be written to the register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.