Enforcement of memory reference object loading indirection
US10846016B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2017 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Feb 26, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one example in accordance with the present disclosure, enforcement of memory reference object loading indirection is described. According to a method, at a register, it is determined from an indirection counter of a first memory referencing object (MRO) in one of a number of registers of a processor of the computing device, whether a second MRO is loadable. When the indirection counter of the first MRO indicates a second MRO is loadable, the second MRO is loaded from the memory device to one of the number of registers. The second MRO also includes an indirection counter. The indirection counter of the loaded second MRO is changed, at the register that contains it, based on the indirection counter of the first MRO to enforce a degree of MRO loading indirection. Further, MRO loading is prohibited when an indirection counter reaches zero by invalidating a capability counter of a subsequent MRO at the register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.