Secure forking of error telemetry data to independent processing units
US10846162B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2018 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Jul 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/3528
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Utilities (e.g., systems, methods, etc.) that make use of a secure input/output (I/O) channel between system firmware (e.g., BIOS) and the SP to allow the BIOS to securely send data (e.g., error data) for secure consumption by the SP while preventing or limiting other sources from sending falsified data or the like the SP. The secure I/O channel includes interface hardware (e.g., Field-programmable gate array (FPGA)) that is configured to be unlocked by the BIOS using a security key received from a key generator over a separate security channel. After such data is securely sent to the interface hardware, the BIOS may then pass error interrupt(s) to the OS for performing of any necessary recovery actions. At any appropriate time, the SP may read or consume error data from the memory register of the interface hardware and perform any appropriate diagnoses and/or handling of the error data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.