Providing reconfigurable fusion of processing elements (PEs) in vector-processor-based devices
US10846260B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2018 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Nov 29, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Providing reconfigurable fusion of processing elements (PEs) in vector-processor-based devices is disclosed. In this regard, a vector-processor-based device provides a vector processor including a plurality of PEs and a decode/control circuit. The decode/control circuit receives an instruction block containing a vectorizable loop comprising a loop body. The decode/control circuit determines how many PEs of the plurality of PEs are required to execute the loop body, and reconfigures the plurality of PEs into one or more fused PEs, each including the determined number of PEs required to execute the loop body. The plurality of PEs, reconfigured into one or more fused PEs, then executes one or more loop iterations of the loop body. Some aspects further include a PE communications link interconnecting the plurality of PEs, to enable communications between PEs of a fused PE and communications of inter-iteration data dependencies between PEs without requiring vector register file access operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.