Low power and area ternary content addressable memory circuit
US10847224B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2019 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Jul 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, devices, and methods are provided for implementing a low power and area ternary content addressable memory (TCAM). The TCAM comprises a plurality of memristor-based TCAM (mTCAM) cells, each consisting of two memristors and two transistors. The first and second memristors are connected in series, with a first end of the first memristor connected to a first data line, first end of the second memristor connected to a second data line, and the second ends of the resistors connected together at a common node. The drain of a programming transistor is connected to the common node, with the source connected to a third data line, and the gate connected to a word line. Common node is further connected to the gate of a match-line transistor, such that if a mismatch is detected common node applies a voltage to the gate to pull-down the voltage on a pre-charged match line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.