Stress compensation and relief in bonded wafers
US10847419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2018 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Mar 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a process for manufacturing individual die devices, with a desired or predicted amount of flatness, from a bonded wafer process. The flatness of a bonded wafer is measured at point in the wafer manufacturing process. This measurement is compared to a value predetermined by an empirical analysis of previous devices made by the same process. If the flatness of the bonded wafer is not at the predetermined value, then one or more compensation layers are provided to the bonded wafer to obtain the predetermined flatness value. Once obtained, subsequent processing is performed and the resulting individual dies are obtained with the desired flatness characteristic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.