CTE compensation for wafer-level and chip-scale packages and assemblies

US10847469B2 · kind B2 · utility

Assignee

• Cubic Corporation · US

Inventors

• Kenneth Vanhille · Albuquerque, US
• Aaron C. Caba · Blacksburg, US
• Masud Beroz · Livermore, US
• Jared W. Jordan · Sahuarita, US
• Timothy Amis Smith · Durham, US
• Anatoliy O. Boryssenko · Granby, US
• Steven E. Huettner · Billerica, US

Key dates

• Filing date: Jul 17, 2017
• Grant date: Nov 24, 2020
• Expiry date: Jul 17, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15311
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A microelectronic structure having CTE compensation for use in wafer-level and chip-scale packages, comprising a plurality of substrate tiles each having a generally planar upper surface, the upper surfaces of the tiles disposed within a common plane to provide a generally planar grid of the tiles, each respective pair of adjacent tiles having a gap disposed therebetween.