Latch with redundancy and circuitry to protect against a soft error
US10848134B2 · kind B2 · utility
1Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2015 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Oct 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus is described having a latch circuit. The latch circuit includes redundant data inputs, redundant data outputs, redundant clock inputs and circuitry to self-correct a soft-error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.