Receiver signal chains with low power drivers and driver optimization
US10848169B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2019 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Mar 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Non-idealities of input circuitry of a receiver signal chain can significantly degrade the overall performance of the receiver signal chain. To meet high performance requirements, the input circuitry is typically implemented with power hungry circuitry in a different semiconductor technology from the analog-to-digital converter that the input circuitry is driving. With suitable optimization techniques, performance requirements on the input circuitry can be reduced while meeting target performance of the receiver signal chain. Specifically, optimization techniques can compensate for input frequency-dependent properties and/or amplitude-dependent properties of the input circuitry. In some cases, reducing performance requirements on the input circuitry means that the input circuitry can be implemented in the same semiconductor technology as the analog-to-digital converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.