Performance optimization and support compatibility of data compression with hardware accelerator
US10848179B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2019 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Oct 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/4043
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
One embodiment provides a computer implemented method of data compression using a hardware accelerator. A first thread pool for compression jobs, and a first polling thread is allocated for polling the status of a hardware accelerator. A compression thread is retrieved from the first thread pool in response to a compression request from a file system. Multiple source data buffers from the file system are aggregated into a compression unit, and a scatter gather list and destination buffer are submitted to the hardware accelerator. A checksum of result data is calculated from the destination buffer. A zlib header is added to the result data, and the checksum is added as a zlib footer to the result data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.