Adaptive power down of intra-chip interconnect
US10852810B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2019 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Mar 6, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising a plurality of last-level caches, a plurality of processor cores configured to access data in the plurality of last-level caches, and an interconnect network. The plurality of last-level caches can be placed in at least a high cache-power consumption mode and a low cache-power consumption mode. The plurality of last-level caches includes a first last-level cache and a second last-level cache. The interconnect network comprises a plurality of links that can be placed in at least a high link-power consumption mode and a low link-power consumption mode. The interconnect network is configured to cause a first subset of the plurality of links to be placed in the low link-power consumption mode based at least in part on the first last-level cache being in the low cache-power consumption mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.