Structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and burst reordering
US10852956B1 · kind B1 · utility
2Cited by
0References
20Claims
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Key dates
| Filing date | Jun 30, 2016 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Oct 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40618
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention provide a novel structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and DRAM burst reordering. Where the external per-bank refresh removes some of the unpredictable nature of PBR commands and DRAM burst reordering provides for efficient utilization of memory bandwidth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.