Memory controller and memory controlling method where number of commands (executed by the memory controller prior to releasing host memory) is adjusted based on transmission speed of interface to host
US10852991B1 · kind B1 · utility
2Cited by
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15Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 23, 2019 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Aug 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes an interface circuit and a control circuit. The interface circuit is configured to communicate with a host device. When the control circuit finishes executing N commands from the host device, the memory controller notifies the host device to release corresponding memory in the host device corresponding to the N commands, and N is a positive integer. The control circuit compares a data transmission speed of the interface circuit with a predetermined value to generate a comparison result, and the control circuit adjusts a value of N based on the comparison result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.