Processor suspension buffer and instruction queue
US10853070B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2018 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Dec 7, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a processing engine, an address queue, an address generation unit, and logic circuitry. The processing engine is configured to process instructions that access data in an external memory. The address generation unit is configured to generate respective addresses for the instructions to be processed by the processing engine, to provide the addresses to the processing engine, and to write the addresses to the address queue. The logic circuitry is configured to access the external memory on behalf of the processing engine while compensating for variations in access latency to the external memory, by reading the addresses from the address queue, and executing the instructions in the external memory in accordance with the addresses read from the address queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.