Hiding latency of multiplier-accumulator using partial results
US10853448B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2017 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Jul 11, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computational apparatus includes a memory, which is configured to contain multiple matrices of input data values. An array of processing elements is configured to perform multiplications of respective first and second input operands and to accumulate products of the multiplication to generate respective output values. Data access logic is configured to select from the memory a plurality of mutually-disjoint first matrices and a second matrix, and to distribute to the processing elements the input data values in a sequence that is interleaved among the first matrices, along with corresponding input data values from the second matrix, so as to cause the processing elements to compute, in the interleaved sequence, respective convolutions of each of the first matrices with the second matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.