System, method and computer-accessible medium for satisfiability attack resistant logic locking
US10853523B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2017 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Mar 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exemplary embodiment of the present disclosure can include, for example, a logic-locking circuit (“SARLock”), which can include a logic cone(s) receiving a distinguishing input pattern(s) (DIP), a comparator(s) receiving the DIP(s) and a key value(s), and a logic gate(s) connected to an output of the logic cone and to an output of the comparator. A mask(s) can be connected to the comparator(s) and the logic gate(s). The logic gate(s) can be a XOR gate(s). The comparator(s) can be configured to flip a signal(s) based on a combination of the DIP(s) and the key value(s). A mask(s) can be connected to the comparator(s) and the logic gate(s), which can be configured to prevent the flipped signal(s) from being asserted for a correct key value(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.