Vias with multiconnection via structures
US10853553B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2019 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Jun 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Improving an initial via in a circuit comprises: obtaining layout information associated with an initial via structure in a circuit, the initial via comprising an initial lower metal enclosure and an initial upper metal enclosure connected by an initial cut; determining layout information associated with a multiconnection via structure comprising a plurality of sibling vias having at least one additional upper metal enclosure and at least one additional lower metal enclosure; updating the layout information associated with the initial via with the layout information associated with the multiconnection via structure; and outputting the updated layout information. The plurality of sibling vias are connected by a plurality of corresponding sibling cuts, and the multiconnection via structure has lower resistance than the initial via structure. In some embodiments, the multiconnection via is efficiently represented in using a master template.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.