Patent · US Active

Current-starved delay circuitry

US10854264B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Surya Prakash Gupta · Korba, IN
Piyush Jain · Irvine, US
El Mehdi Boujamaa · Grasse, FR

Key dates

Filing date	Mar 5, 2019
Grant date	Dec 1, 2020
Priority date	—
Expiry date	Mar 5, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/1673
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein refer to an integrated circuit having a sense amplifier that operates with a clock signal, and the sense amplifier may be biased with a bias signal that affects duration of the clock signal. The integrated circuit may include a delay circuit coupled to the sense amplifier, and the delay circuit may turn-off the clock signal. The delay circuit may have a current-starved delay stage that receives an input signal having a falling edge and provides a current-starved delay signal biased by the bias signal that also biases the sense amplifier.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.